Running Sparse and Low-precision Neural Networks: When Algorithm Meets Hardware

·         Speaker: Prof. Yiran Chen (陳怡然), Dept. of Electrical and Computer Engineering, Duke University

·         Host: Prof. Youn-Long Lin, Dept. of CS, NTHU

·         Date: Dec. 14, 2017 | 4:00-5:30pm

·         Venue: NTHU Delta 109

Please sign up at goo.gl/SFBuqa.

Abstract:

Rapid increase of computation cost consumed in training and testing of deep neural networks (DNNs) inspired many acceleration techniques. Reducing topological complexity and data representation of neural networks are two approaches popularly adopted in deep learning algorithm society. In general, many connections in DNNs can be pruned and the synaptic weights can be represented using low-precision without/with minimum impact on inference accuracy. However, these algorithm-level techniques often ignore the practical scenarios when they are deployed onto hardware computing platforms, e.g., the increase in the random accesses to memory hierarchy. On the contrary, hardware society often has limited understanding about the expectations from algorithm society and hence, makes many unrealistic assumptions during hardware designs. In this talk, we will discuss this mismatch and show how we can solve this problem through an interactive design practice across both software and hardware regimes.

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