清華大李政崑教授將於12/21在清華大學國際會議廳(綜二館8F)舉辦『OpenCL編譯器與課程論壇』，

論壇將邀請AMD 朱子青博士蒞臨演講，議程表請詳閱附件。

活動日期：100年12月21日(三) 9:00~15:30
活動地點：清大 國際會議廳

活動網址：http://esw.cs.nthu.edu.tw/

報名網址：http://esw.cs.nthu.edu.tw/signup/signup.php?ActivityID=143

誠摯邀請您報名參加！

對於活動如有任何疑問，歡迎洽詢 03-5742311 劉晏君小姐 (bettyliu@pllab.cs.nthu.edu.tw)

繳費方式：

1. 以郵局匯票或支票(僅接受即期支票) 【匯票戶名：國立清華大學 支票戶名：國立清華大學】
2. 現場繳費

匯票寄送地址：30013 新竹市光復路二段101號　國立清華大學 台達館R303 積體電路中心　劉晏君小姐收

Talk Title: Fusion System Architecture and Heterogeneous Computing Programming

Speaker’s Bio:

Roy D.C. Ju has been a compiler architect and a Fellow at Advanced Micro Devices since 2006. He has been driving the optimization technology for high-performance, cross-platform compilation for AMD multi-core CPU and GPU architectures. He is currently the compiler architect for the Fusion System Architecture project. Prior to joining AMD, he made a brief stop at Google Inc. working on a distributed system and Google Desktop. From 1999 to 2005, he was a senior researcher and the manager of Compiler Technology group at the Programming System Lab in the Microprocessor Technology Labs, Intel Corp. He led an effort in innovating programming and compiler technology for multi-core architectures, including a multi-core network processor. He had been the architect of an IA-64 open source research compiler (Open Research Compiler), which provided an infrastructure for compiler and architecture research on IA-64 to the research and open source communities. He was with the Hewlett-Packard Company from 1994 to 1999, where he was a project lead in designing and developing an optimizing compiler for IA-64. He worked at IBM from 1992 to 1994 in developing a then state-of-the-art Fortran 90 optimizing compiler. His primary research interests include compiler optimizations, optimization for memory hierarchy, program analysis, computer architecture, multi-core systems, and parallel processing. He received his B.S. in Electrical Engineering from National Taiwan University in 1984. He received his M.S. and Ph.D. in Electrical and Computer Engineering from the University of Texas at Austin in 1988 and 1992, respectively. He currently holds 24 U.S. patents and has published more than 60 journal and conference papers in various areas, including array language optimizations, compilation for instruction-level parallelism, cache optimization, coarse-grained parallelization, etc. He has served on the program committees of a number of conferences, such as MICRO-33, MICRO-35, PLDI '01, MSP '02, CGO '03, '04, '05, LCTES '05, COCV '05, Open64 Workshop '08 and '09, EUC '09 and '10, PPoPP '11, and PACT'11. He was a General Co-Chair of CGO '07.